Virtual ground circuit for reducing SRAM standby power

ABSTRACT

A method of operating a memory circuit having a plurality of blocks of memory cells ( 400 - 404 ) is disclosed. The method includes storing data in the plurality of blocks of memory cells. A first block of memory cells ( 400 ) is selected in response to a first address signal (RA Y0 ). A row of memory cells ( 430 - 436 ) in the first block of memory cells is selected in response to a second address signal (RA X0 ). A first voltage is applied to a first power supply terminal ( 412 ) of the first block of memory cells in response to the first address signal. A second voltage different from the first voltage is applied to a first power supply terminal ( 412 ) of another block of memory cells ( 402 ) of the plurality of blocks of memory cells. Data is retained in the other block of memory cells.

FIELD OF THE INVENTION

This invention generally relates to electronic circuits, and morespecifically to power reduction in semiconductor integrated circuits.

BACKGROUND OF THE INVENTION

The continuing popularity of portable electronic devices presentsmanufacturers with contrary goals. Battery capacity is dependent uponbattery size and weight. Thus portable electronic devices could be madeto operate a longer time between battery changes or recharging if thesedevices included heavier batteries with greater capacity. On the otherhand, portable electronic devices would be more popular and more widelyused if they were lighter. However, lighter weight translates intoreduced battery capacity and reduced operating times. A large reductionin size of wireless telephones has taken place without significantreduction in operating times. While improvements in batteries haveincreased their capacity per unit weight, most of the improvement inoperating time and reduction in device weight has come from improvementsin the power consumption of the electronics. Many improvements havetaken place in integrated circuit manufacture that have reduced theamount of power consumed by the electronics. Additional improvementshave taken place by selective powering of portions of the electronics.To a large degree much of the advantage of selectively powering amicrocontroller unit or a digital signal processor have already beenrealized by current state of the art devices. Thus manufacturers seekadditional areas for power consumption reduction.

This additional area may be either a cache or main memory. Many portableelectronic devices include substantial amounts of memory. Power savingsmay be gained by reducing leakage current in either nonvolatile orvolatile memory in respective active and standby operating modes. Wei etal., “Design and Optimization of Low Voltage High Performance DualThreshold CMOS Circuits,” 35^(th) Design Automation Conference Proc.,489-494 (1998) disclose a circuit and method for reducing leakagecurrent using a dual threshold voltage process. This dual thresholdvoltage, however, requires a separate process step and may slow normalcircuit operation. Powell et al., “Gated-Vdd: A Circuit Technique toReduce Leakage in Deep-Submicron Cache Memories,” Proc. Int. Symp. LowPower Electronics and Design (ISLPED), 90-95 (2000) disclose adynamically resizable instruction (DRI) cache wherein a gated-groundnMOS transistor turns off unused portions of the instruction cache afterapplication requirements are identified. Agarawal et al., “A Single-VtLow-Leakage Gated-Ground Cache for Deep Submicron,” IEEE J. Solid-StateCircuits, vol. 38, no. 2, 319-328 (February 2003) disclose a dataretention gated-ground cache (DRG cache) that turns off the cache duringstandby mode to conserve power. However, significant array noise may begenerated when these rows of memory cells are restored to active mode.Moreover, initial access time may be reduced while full power isrestored. The process of fully powering these memory circuits typicallyrequires much more time than that required for a memory access in thefully powered state. Thus, memory access time from a low power orstandby state includes both the time required to power up the memorycircuit and the normal access time. However, access times of thesememories remains important, so it may not be feasible to completely shutthe memory down to conserve power.

SUMMARY OF THE INVENTION

In accordance with a preferred embodiment of the invention, there isdisclosed a method of operating a memory circuit having a plurality ofblocks of memory cells. Data are stored in the plurality of blocks ofmemory cells. A first block of memory cells is selected in response to afirst address signal. A row of memory cells in the first block of memorycells is selected in response to a second address signal. A firstvoltage is applied to a first power supply terminal of the first blockof memory cells in response to the first address signal. A secondvoltage different from the first voltage is applied to the first powersupply terminal of another block of memory cells of the plurality ofblocks of memory cells in response to the first address signal. Data isretained in unselected blocks of memory cells.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing features of the present invention may be more fullyunderstood from the following detailed description, read in conjunctionwith the accompanying drawings, wherein:

FIG. 1 is a block diagram of a wireless telephone which is an example ofa portable electronic device which may advantageously employ the presentinvention;

FIG. 2 is a block diagram of a static random access memory (SRAM) as maybe used in the volatile memory circuit 148 of FIG. 1;

FIG. 3 is a schematic diagram of a 6-T static random access memory cellas may be used in the SRAM of FIG. 2;

FIG. 4 is a schematic diagram of an embodiment of the present inventionof SRAM array 202 of FIG. 2 having a virtual ground switch selectedaccording to a predecoded block address;

FIG. 5 is a schematic diagram of another embodiment of the presentinvention of SRAM array 202 of FIG. 2 having a virtual ground switchselected according to a predecoded block address and a row segmentaddress;

FIG. 6A is a second embodiment of a virtual ground switch according tothe present invention;

FIG. 6B is a third embodiment of a virtual ground switch according tothe present invention; and

FIG. 6C is a fourth embodiment of a virtual ground switch according tothe present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Referring to FIG. 1, there is a block diagram of a wireless telephone asan example of a portable electronic device which could advantageouslyemploy this invention. Wireless telephone 100 includes antenna 102,radio frequency transceiver 104, baseband circuits 106, microphone 108,speaker 110, keypad 112, and display 114. The wireless telephone ispreferably powered by a rechargeable battery (not shown) as is wellknown in the art. Antenna 102 permits wireless telephone 100 to interactwith the radio frequency environment for wireless telephony in a mannerknown in the art. Radio frequency transceiver 104 both transmits andreceives radio frequency signals via antenna 102. The transmittedsignals are modulated by the voice/data output signals received frombaseband circuits 106 on bus 120. The received signals are demodulatedand supplied to baseband circuits 106 as voice/data input signals on bus120. An analog section 130 includes an analog to digital converter 132connected to microphone 108 to receive analog voice signals. The analogto digital converter 132 converts these analog voice signals to digitaldata and applies them to digital signal processor 140 via bus 120.Analog section 130 also includes a digital to analog converter 134connected to speaker 110. Speaker 110 provides the voice output to theuser. Digital section 106 is embodied in one or more integrated circuitsand includes a microcontroller unit 142, a digital signal processor 140,nonvolatile memory circuit 146, and volatile memory circuit 148.Nonvolatile memory circuit 146 may include read only memory (ROM),ferroelectric memory (FeRAM), FLASH memory, or other nonvolatile memoryas known in the art. Volatile memory circuit 148 may include dynamicrandom access memory (DRAM), static random access memory (SRAM), orother volatile memory circuits as known in the art. Microcontroller unit142 interacts with keypad 112 to receive telephone number inputs andcontrol inputs from the user. Microcontroller unit 142 supplies thedrive function to display 114 to display numbers dialed, the currentstate of the telephone such as battery life remaining, and receivedalphanumeric messages. Digital signal processor 140 provides real timesignal processing for transmit encoding, receive decoding, errordetection and correction, echo cancellation, voice band filtering, etc.Both microcontroller unit 142 and digital signal processor 140 interfacewith nonvolatile memory circuit 146 via bus 144 for program instructionsand user profile data. Microcontroller unit 142 and digital signalprocessor 140 also interface with volatile memory circuit 148 via bus144 for signal processing, voice recognition processing, and otherapplications.

Referring to FIG. 2, there is a block diagram of a static random accessmemory circuit as may be used in the volatile memory circuit 148 ofFIG. 1. The static random access memory circuit includes a timing andcontrol circuit 200 coupled to receive a clock enable signal CKE, asystem clock signal CLK, and a read/write signal R/W. During a standbymode of operation, clock enable signal CKE is at a logic low level.During an active mode of operation, clock enable signal CKE is at alogic high level. The static random access memory circuit of the presentinvention advantageously makes a transition from a standby mode to anactive mode without generating significant array noise and withoutsignificant first access time penalty as will be explained in detail.

In active mode, the timing and control circuit 200 generates internalcontrol signals (not shown) to control read and write operations of thestatic random access memory. An address applied to bus 212 includes rowand column address bits. The row address bits are applied to row decodercircuit 214. The column address bits are applied to column decodercircuit 206. The row decoder circuit activates a wordline in response tothe row address bits, thereby selecting a row of memory cells from thestatic random access memory array 202. The column decoder circuit 206selects a column of memory cells in response to the column address bitson bus 212. A memory cell at the intersection of the selected row andcolumn produces data to output circuit 208 during a read operation.Alternatively, the memory cell at the intersection of the selected rowand column receives data from input circuit 210 during a writeoperation.

Turning now to FIG. 3, there is a schematic diagram of memory cell asmay be used in the SRAM array 202 of FIG. 2. The memory cell includes alatch formed by P-channel transistors 301 and 302 and N-channeltransistors 303 and 304. P-channel transistor 301 is connected toN-channel transistor 303 to form a first inverting circuit having anoutput at terminal 316 and having an input at terminal 318. Likewise,P-channel transistor 302 is connected to N-channel transistor 304 toform a second inverting circuit having an output at terminal 318 andhaving an input at terminal 316. Each of the first and second invertingcircuits, therefore, has an output connected to the input of the otherinverting circuit to retain data in a latched state as long as power isapplied to the memory cell. The source terminals of P-channeltransistors 301 and 302 are connected to a power supply terminal whichis preferably a positive Vdd or Varray power supply voltage. The sourceterminals of N-channel transistors 303 and 304 are connected to virtualground terminal 314. The memory cell also includes N-channel accesstransistors 305 and 306. The current path of N-channel transistor 305 iscoupled between bitline BL 308 and output terminal 316. The current pathof N-channel transistor 306 is coupled between complementary bitline/BL310 and output terminal 318. Control gates of N-channel transistors 305and 306 are connected to wordline WL 320. By convention, all memorycells coupled to a common wordline form a row of memory cells. Likewise,all memory cells coupled to common bitlines and complementary bitlinesform a column of memory cells.

In active mode, virtual ground terminal 314 is connected to a referencepower supply terminal by a virtual ground switch for memory read orwrite operations as will be discussed in detail. This reference powersupply terminal is preferably Vss or ground. Bitline BL andcomplementary bitline/BL are initially precharged to a logic high level,and wordline WL is at a low logic level. Data is stored in the latchportion of the memory cell such that one transistor of each inverter ison while the other is off. For example, if the memory cell stores alogical one, output terminal 316 produces a high logic level “1” andoutput terminal 318 produces a low logic level “0”. For this data state,therefore, P-channel transistor 301 is on, and N-channel 303 is off.P-channel transistor 302 is off, and N-channel transistor 304 is on.Even when off, however, these transistors conduct significantsubthreshold leakage current under weak inversion. N-channel transistor306 and P-channel transistor 302 comprise parallel subthresholdconduction paths (1) and (2) to output terminal 318. N-channeltransistor 303 comprises another subthreshold conduction path (3) tovirtual ground terminal 314. Subthreshold leakage current is dominatedby diffusion current rather than drift current. Thus, it is a strongfunction of a difference between gate-to-source voltage Vgs andthreshold voltage Vt of a transistor. As a result, subthreshold currentdecreases exponentially as Vgs falls below Vt. The present inventionadvantageously minimizes this subthreshold leakage current during activemode by selectively activating virtual ground switches for those memorycells where read or write operations are possible. Other virtual groundswitches remain off, thereby reducing subthreshold leakage current.

Moreover, in a standby mode, all virtual ground switches are off,thereby greatly reducing standby power of the memory circuit. In thismode, voltage at virtual ground terminal 314 is approximately athreshold voltage above reference power supply voltage Vss or ground.This increase in voltage at the virtual ground terminal produces acorresponding increase in voltage at output terminals 316 and 318. Theprecise voltage at virtual ground terminal is not critical. Referringback to the previous example, it is important that the voltage at outputterminal 316 is an N-channel Vt above the voltage at virtual groundterminal 314 so that N-channel transistor 304 remains on. It is alsoimportant that the voltage at output terminal 318 is a P-channel Vtbelow power supply voltage Vdd 312 so that P-channel transistor 301remains on. Thus, data stored in the memory cell is maintained when therespective virtual ground switch is off. The voltage increase at virtualground terminal 314 increases the body effect and correspondingtransistor threshold voltage Vt of N-channel transistor 303. Thecorresponding voltage increase at output terminal 318 increases the bodyeffect and corresponding transistor threshold voltage Vt of N-channeltransistor 306. Both effects increase Vt and reduce Vgs-Vt andsubthreshold current through N-channel transistors 303 and 306,respectively. The increase in voltage at output terminal 316 directlydecreases Vgs-Vt of P-channel transistor 302, thereby reducingsubthreshold current.

Turning now to FIG. 4, there is a static random access memory array ofthe present invention. The memory array includes m+1 memory blocks400,402, and 404, where m is a positive integer. Each memory block isselected by a respective predecoded address signal RA_(Y0), RA_(Y1), andRA_(Ym). Each of the memory blocks includes n+1 rows of memory cells andcorresponding row decode circuits, where n is a positive integer. Forexample, memory block 400 includes a row decode circuit formed by NANDgate 406 and inverter 408. NAND gate 406 receives address signal RA_(X0)to specifically select wordline 410. Address signal RA_(X0) ispreferably a group of least significant row address bits. NAND gate 406also receives address signal RA_(Y0) which is preferably a group of mostsignificant row address bits. Taken together, address signals RA_(X0)and RA_(Y0) select memory block 400 and wordline 410. The memory cellsof each block are arranged in columns. For example, memory cells 430 and440 are arranged in a column connected to bitlines 414 and 416. Avirtual ground terminal 412 is common to all memory cells in memoryblock 400 such as memory cells 430-436 in a first row and memory cell440 in a second row. All of the blocks of memory cells share referencevoltage supply lines 422, which are preferably distributed through thememory array. The virtual ground terminal 412 is selectively connectedto these reference voltage supply lines in an active mode by a virtualground switch formed by transistors 418 and 420. These virtual groundswitch transistors 418 and 420 are selectively enabled by address signalRA_(Y0) when memory block 400 is enabled in an active mode. Respectivevirtual ground switches of other unselected memory blocks 402 and 404remain off in response to their respective predecoded address signalsRA_(Y1), and RA_(Ym).

In operation, the memory circuit is initially in standby mode and allwordlines of each memory block are at a logic low level. All virtualground switches are off in response to respective predecoded addresssignals RA_(Y0-m). In this mode, the voltage at respective virtualground terminals of each memory block, such as terminal 412, increasesto approximately a threshold voltage positive with respect to referencevoltage Vss or ground 422. This increase results from a ratio of memorycell subthreshold leakage to virtual ground subthreshold leakage withineach respective memory block. The virtual ground switch subthresholdleakage is preferably greater than or equal to the memory cellsubthreshold, so that a saturation voltage at virtual ground terminal412 is less than one-half of power supply voltage Vdd. This increasedvoltage advantageously decreases standby power of the memory circuit aspreviously discussed.

Upon a transition to active mode such as a read or write operation,address signals RA_(X0-n) and RA_(Y0), for example, are applied to therow decode circuits of block 400. The common virtual ground terminal ofmemory block 400 is quickly discharged to reference voltage Vss. Virtualground terminals of other unselected memory blocks 402-404 remain attheir saturation voltages. A product of the discharge current of block400 and metal resistance induces a brief voltage spike on the powersupply reference voltage lines 422. Such a voltage spike is oftenreferred to as array noise and may capacitively couple to signal linessuch as adjacent bitlines and create a data error. The presentinvention, however, advantageously minimizes the magnitude of thisvoltage spike by activating only one of the memory blocks correspondingto a respective predecoded address signal. Moreover, due to therelatively small magnitude of the voltage spike, no significant timedelay is required before a read operation of a selected memory cell maybe performed.

Referring now to FIG. 5, there is a single memory block 500 showinganother embodiment of the present invention. As with the example of FIG.4, memory block 500 is preferably one of m memory blocks in a memoryarray. Memory block 500 includes n rows of segmented wordlines. Eachsegmented wordline includes a global wordline, for example, globalwordline 504 and wordline segments 508 and 512. Memory block 500 isselected from a memory array by predecoded address signal RA_(Y0).Global wordline 504, for example, is selected within memory block 500 byAND gate 502 in response to address signal RA_(X0). As with block 400,RA_(X0) and RA_(Y0) are preferably least and most significant rowaddress bits, respectively. A segment select signal on lead 524 or lead528 selects one of wordline segments 508 and 512 by enabling one of ANDgates 506 and 510. Data are transmitted to and from a memory cell suchas memory cell 530 by bitlines 514 and 516. Memory cells correspondingto each group of wordline segments in memory block 500 include arespective virtual ground terminal. For example, memory cells 530 and532 are connected to virtual ground terminal 525. Likewise, memory cells534 and 536 are connected to virtual ground terminal 527. The virtualground switches operate as previously described except that each virtualground switch is enabled by both a predecoded block select addresssignal and a segment select signal. For example, N-channel transistors520 and 521 form a virtual ground switch for virtual ground terminal525. N-channel transistors 522 and 523 form a virtual ground switch forvirtual ground terminal 527. Both virtual ground switches selectivelyconnect their respective virtual ground terminals to reference powersupply lines 526, which are common to all m memory blocks of the memoryarray.

In operation, all memory blocks are initially in standby mode aspreviously described with respect to FIG. 4. Upon a transition to activemode such as a read or write operation, address signal RA_(X0) andRA_(Y0), for example, are applied to AND gate 502 to select block 500and global wordline 504. A segment select signal on lead 524 is appliedto AND gate 506. Thus, wordline segment 508 goes to a high logic levelwhile wordline segment 512 remains low. The common virtual groundterminal 525 of memory block 500 is quickly discharged to referencevoltage Vss through transistors 520 and 521. Virtual ground terminals ofunselected wordline segment groups and other memory blocks remain attheir saturation voltages. A voltage spike induced by this discharge,however, is substantially less than that of FIG. 4, since a singlewordline segment group shares all reference power supply lines 526. Theembodiment of FIG. 5, therefore, provides a further reduction in arraynoise and improved first access time.

Referring now to FIGS. 6A-6C, there are three alternative embodiments ofvirtual ground switches that may be used with the memory arrays of FIGS.4 and 5. In each case, terminal 600 is the virtual ground terminal,N-channel transistor 602 connects the virtual ground terminal toreference voltage supply Vss, and a high logic level signal at terminal606 selectively enables the virtual ground switch. In operation, theembodiment of FIG. 6A selectively connects virtual ground terminal 600to reference voltage supply Vss through P-channel transistor 604 whenthe signal at terminal 606 is at a low logic level. Thus, the virtualground terminal remains at a saturation voltage of approximately aP-channel threshold voltage positive with respect to reference voltagesupply Vss. The embodiment of FIG. 6B connects virtual ground terminal600 to reference voltage supply Vss through N-channel transistor 605configured as a diode. Thus, the virtual ground terminal remains at asaturation voltage of approximately an N-channel threshold voltage Vtpositive with respect to reference voltage supply Vss when the signal atterminal 606 is at a low logic level. Finally, in the embodiment of FIG.6C the signal on lead 606 is inverted and applied to a control gate ofN-channel transistor. Thus, N-channel transistor 608 selectivelyconnects virtual ground terminal 600 to a reference voltage at lead 610when a signal at lead 606 is low.

While this invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications and combinations of theillustrative embodiments, as well as other embodiments of the invention,will be apparent to persons skilled in the art upon reference to thedescription. For example, advantages of the present invention might berealized by a virtual power supply line rather than a virtual groundline. Each switching circuit would be inserted between the Vdd or Varraypower supply and a common source terminal of the P-channel transistorsof the memory cell. Furthermore, application of the present invention isnot strictly limited to memory cells. Advantages of the presentinvention might be realized by reducing subthreshold current through anytransistor circuit such as inverter 408 (FIG. 4) during standby mode. Inview of the foregoing discussion, it is intended that the appendedclaims encompass any such modifications or embodiments.

1. A method of operating a memory circuit, comprising the steps of: selecting a first block of memory cells in response to a first address signal; selecting a row of memory cells in the first block of memory cells in response to a second address signal; applying a first voltage to a first reference power supply ground terminal of the first block of memory cells in response to the first address signal; applying a second voltage different from the first voltage to a first reference power supply ground terminal of another block of memory cells of the plurality of blocks of memory cells in response to the first address; and using a virtual ground switch for the applying of the first voltage or the second voltage, and the virtual ground switch comprises two transistors operating together to set an output terminal of the virtual ground switch at a threshold voltage of a N-channel or P-channel transistor.
 2. A method as in claim 1, further comprising a step of letting a virtual ground terminal of the first block of memory cells increase to a threshold voltage above the first voltage.
 3. A method as in claim 1, comprising the steps of: unselecting the first block of memory cells in response to a control signal; and applying the second voltage to the first block of memory cells.
 4. A method as in claim 1, wherein the second voltage is positive with respect to the first voltage.
 5. A method as in claim 1, wherein the memory circuit is a static random access memory circuit.
 6. A method as in claim 1, wherein the step of selecting a row of memory cells comprises selecting a segment of a global row of memory cells in response to a third address signal, and wherein the step of applying the second voltage comprises applying the second voltage in response to the first and third address signals.
 7. A method as in claim 1, wherein the step of selecting a row of memory cells comprises applying the first voltage to a drive circuit in response to the second address signal.
 8. A memory circuit, comprising: a memory array having a plurality of blocks of memory cells, each block having a respective plurality of rows of memory cells, each memory cell having a respective first power supply terminal; a first row dedode circuit coupled to the respective plurality of rows of memory cells of a first block of memory cells and coupled to receive a first address signal; a first switching circuit arranged to selectively connect the first power supply terminal of the respective plurality of rows of memory cells of the first block of memory cells to a second power supply terminal in response to the first address signal; a second row decode circuit coupled to the respective plurality of rows of memory cells of a second block of memory cells and coupled to receive a second address signal; and a second switching circuit arranged to selectively connect the first power supply terminal of the respective plurality of rows of memory cells of the second block of memory cells to the second power supply terminal in response to the second address signal.
 9. A memory circuit as in claim 8, wherein the memory cells are static random access memory cells.
 10. A memory circuit as in claim 8, wherein each of the first address signal corresponds to the first block of memory cells, and wherein the second address signal corresponds to the second block of memory cells.
 11. A memory circuit as in claim 8, wherein each switching circuit comprises: a P-channel transistor having a current path connected between the first and second power supply terminals; and an N-channel transistor having a current path connected between the first and second power supply terminals.
 12. A memory circuit as in claim 8, wherein each switching circuit comprises: a first N-channel transistor having a current path connected between the first and second power supply terminals; and a second N-channel transistor having a current path connected between the first and second power supply terminals and having a control gate connected to one end of the current path.
 13. A memory circuit as in claim 8, wherein each switching circuit comprises: a first N-channel transistor having a current path connected between the first and second power supply terminals; and a second N-channel transistor having a current path connected between the first power supply terminal and a third power supply terminal.
 14. A memory circuit as in claim 8, wherein each switching circuit comprises a plurality of transistors connected in parallel.
 15. A memory circuit as in claim 8, wherein the memory cells comprises a latch and two access transistors, wherein the latch comprises two inverting circuits and the two inverting circuits are coupled together at a virtual ground terminal which is coupled to a virtual ground switch.
 16. A method of operating an electronic device, comprising the steps of: selecting a first block of memory cells in response to a first address signal; selecting a row of memory cells in the first block of memory cells in response to a second address signal; applying a first voltage to a first reference power supply ground terminal of the first block of memory cells in response to the first address signal; and applying a second voltage different from the first voltage to a first reference power supply ground terminal of another block of memory cells of the plurality of blocks of memory cells in response to the first address; and using a virtual ground switch for the applying of the first voltage or the second voltage, and the virtual ground switch comprises two transistors operating together to set an output terminal of the virtual ground switch at a threshold voltage of a N-channel or P-channel transistor.
 17. A method as in claim 16, comprising the steps of: unselecting the first block of memory cells in response to a control signal; and applying the second voltage to the first block of memory cells.
 18. A method as in claim 16, wherein a difference between the first voltage and the second voltage is approximately equal to a transistor threshold voltage.
 19. A method as in claim 16, wherein the step of selecting a row of memory cells comprises selecting a segment of a global row of memory cells in response to a third address signal, and wherein the step of applying the second voltage comprises applying the second voltage in response to the first and third address signals.
 20. A method as in claim 16, wherein the step of selecting a row of memory cells comprises applying the first voltage to a drive circuit in response to the second address signal.
 21. A method as in claim 16, wherein the electronic device is a portable electronic device.
 22. A method as in claim 16, wherein the electronic device is a wireless telephone. 